The manuscript proposes a novel delay cell implemented in a four-stage voltage-controlled oscillator (VCO). The design works on the principle of carrier mobility and transistor resistance. The VCO uses dual delay input techniques to improve the frequency of operation. The design is implemented in Cadence 90-nm GPDK CMOS technology and simulated results show that it can operate with a minimum frequency of 3.75 GHz and a maximum frequency of 10 GHz. The power consumption of the circuit at normal temperature is found to be 137 μW. The design shows a good tradeoff between operating frequency, phase noise, and power consumption.