In this present work, the design of a positive high voltage level shifter on System-on-Chips (SoCs) by reducing consumption of power along with propagation delay in the circuitry using appropriate approach is presented. The suggested Level Shifter (LS) may translate input signals to higher nominal voltage levels from considerably lower voltage levels of a device. On account of its ultra-less power dissipation, the proposed LS is well suited in applications that require less power, such as wireless sensor networks and implantable medical equipment. The circuit is realized in CNTFET technology to convert input signals of 1.0 V to output signals of 2.0 V This investigation study computes the power and delay of 32-nm technology CNT-FET based level shifters. We can improve the circuit's overall performance by optimizing the number of nanotubes and other design parameters like CNTs diameter, or pitch.