The development of embedded systems has notably evolved, emphasizing the inclusion of specialized accelerators within microcontrollers to enhance performance and efficiency. A key factor in this integration is the level of connectivity between the central processing unit (CPU) and these accelerators, as well as the specific type of data being handled. This article presents a method to tailor a RISC-V instruction set to specific requirements, enhancing performance while preserving flexibility; this method is explored on a relevant case of study, the Keccak cryptographic hash function. By leveraging the CV32E40PX core and the Core-V eXtension Interface (CV-X-IF), this approach introduces innovative opportunities in accelerator integration. The CV-X-IF simplifies the addition of new instructions to the Instruction Set Architecture (ISA) and streamlines the integration of tightly coupled accelerators. Consequently, these accelerators become more adaptable and can be employed with any RISC-V core, broadening their applicability and potential impact. Experimental results are analyzed and compared with respect to the same accelerator, integrated as loosely-coupled accelerator using the Extendible Accelerator Interface (XAIF). Moreover, the designed RISC-V units are likened to other implementations available in the literature to highlight the potential of the adopted method.