The employment of Charge-Pump Phase-Locked Loops (CP-PLL) has experienced a great increment in several fields during the last decades. One of the most important phases in the design of CP-PLLs is the initial system level design. In this regard, the classical approach focuses on the damping and the bandwidth of the loop, emphasizing the Phase Noise performance. On the other hand, it neglects completely the area occupation of the Loop Filter, which is the largest contributor to the total area. In this work, we propose an area-oriented approach to the system level design of the CP-PLL. It does not replace the classical approach but complements it by providing designers with a method to take area into account from the initial stages of the design. The approach is developed and discussed throughout the paper, and a closed form equation for the total area occupation of the Loop Filter is derived. Moreover, the equation for the Charge Pump current that leads to minimum area for a given bandwidth is also derived. Finally, a discussion on the realization of the Loop Filter with passive components in CMOS technology is also presented.