Many foundries now have a variety of standard CMOS processes available. In microelectromechanical systems (MEMS) as well as in integrated circuits, metallic layers are arranged alternately with dielectric layers in some processes that represent technological advances. The material properties of the metal and dielectric films need to be considered to calculate the performance and suitability of micro devices. This study applies an existing approach to encompass the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. The cantilevers have been designed and implemented with different stacking of metal and dielectric layers for standard CMOS processes. The in-plane thermal displacement of the test cantilevers can be measured to evaluate the CTEs of standard CMOS films.