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This chapter presents techniques for the programmable analysis of RISC-V processors using WAL. The focus on the presented processor analysis techniques lies on two central components of modern systems. First, the analysis of central processing unit (CPU) performance in terms of including an analysis of the processor pipeline is presented. Then, an extensible, automated, and flexible methodology for analyzing cache performance is introduced. Both approaches are evaluated in multiple experiments on several RISC-V processors and core configurations.

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Programmable Analysis of RISC-V Processors Using WAL

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  • 发表日期：

    2025年

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  • Lucas Klemmer,
  • Daniel Große

摘要

This chapter presents techniques for the programmable analysis of RISC-V processors using WAL. The focus on the presented processor analysis techniques lies on two central components of modern systems. First, the analysis of central processing unit (CPU) performance in terms of including an analysis of the processor pipeline is presented. Then, an extensible, automated, and flexible methodology for analyzing cache performance is introduced. Both approaches are evaluated in multiple experiments on several RISC-V processors and core configurations.