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This chapter presents a fully microcoded RISC-V platform based on the one-instruction set computer (OISC) principle. It combines the efficiency of OISC architectures with the established and extensive RISC-V ecosystem. The platform is introduced in two steps. First, a virtual prototype (VP) that facilitates the development of the OISC microcode is presented. Then, the microcode is verified using a formal verification framework based on a model of the OISC architecture.

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A Formally Verified Microcoded RISC-V Platform

  • 章节

  • 发表日期：

    2025年

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  • Lucas Klemmer,
  • Daniel Große

摘要

This chapter presents a fully microcoded RISC-V platform based on the one-instruction set computer (OISC) principle. It combines the efficiency of OISC architectures with the established and extensive RISC-V ecosystem. The platform is introduced in two steps. First, a virtual prototype (VP) that facilitates the development of the OISC microcode is presented. Then, the microcode is verified using a formal verification framework based on a model of the OISC architecture.