The solution of fractional-order chaotic systems can be performed by applying numerical methods that require past values, considered as the memory or history. Practically, any integer-order chaotic system can be transformed to a fractional-order one, and one can find several works doing this transformations as well as the FPGA implementation. In this chapter a fractional-order chaotic system based on a memristor with time delay is described. The Block Verilog descriptions are detailed to infer the usefulness of applying the short memory principle to save hardware resources. Experimental results are given for the FPGA implementation of a PRNG based on the fractional-order chaotic system based on a memristor with time delay. The hardware resources are also provided, so that one can compare the results with the FPGA implementation of integer-order chaotic systems, for instance.