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The industry is producing circuit designs that operate at low voltage (LV) and low power (LP) to meet market demand for efficient portable electronics. Reducing power usage improves device reliability and productivity. CMOS technology is widely used in low- power devices. Lowering the voltage supply quadratically minimizes dynamic power and linearly decreases power leakage. Leakage can cause weak inversion current, which renders it ideal for utilizing standing power. As feature sizes decrease, weak inversion current increases due to leakage and lower sub-threshold voltages. Subthreshold leakage current rises exponentially as a result of the technology size being reduced since the threshold voltage stays lower. The focus of this work is to present an in-depth evaluation and comparison of the DTMOS, MTMOS and LECTOR approaches to decrease power leakage.

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Methods for Mitigating Leakage Power in VLSI Design

  • 会议论文

  • 发表日期：

    2025年

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  • Ramya Belde,
  • K. Niranjan Reddy,
  • E. John Alex

摘要

The industry is producing circuit designs that operate at low voltage (LV) and low power (LP) to meet market demand for efficient portable electronics. Reducing power usage improves device reliability and productivity. CMOS technology is widely used in low- power devices. Lowering the voltage supply quadratically minimizes dynamic power and linearly decreases power leakage. Leakage can cause weak inversion current, which renders it ideal for utilizing standing power. As feature sizes decrease, weak inversion current increases due to leakage and lower sub-threshold voltages. Subthreshold leakage current rises exponentially as a result of the technology size being reduced since the threshold voltage stays lower. The focus of this work is to present an in-depth evaluation and comparison of the DTMOS, MTMOS and LECTOR approaches to decrease power leakage.