An FPGA Accelerated Search Method for Maximum Period NLFSRs
摘要
Maximum period nonlinear feedback shift registers (NLFSRs) are promising building blocks for stream ciphers and pseudo-random number generators. Unfortunately, many fundamental problems related to NLFSRs remain open, and in particular it is not known how to construct simple ones whose periods are of maximum length. In this paper, we describe a search method for finding maximum period NLFSRs. The method is based on using an accelerator implemented on a field programmable gate array (FPGA) to test NLFSR periods, and an initial pruning step that checks for short cycles. We use this method to build build a dataset with complete lists of maximum-period NLFSRs of certain forms up to a length of 32. We also release the source code for our FPGA implementation together with the dataset.