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Cryptography is an essential part of every device involved in the IoT since it ensures the protection of the data against adversaries. The software and hardware implementations of cryptographic algorithms have unwanted leakages that can be leveraged to extract the secret key of the device by a type of attack, namely side-channel attack. This work explores a two-share threshold implementation-based AES hardware accelerator, which is the most efficient technique to withstand first-order power analysis attack with reasonable overhead. The developed ASIC is targeted to work at a frequency of 50 MHz and taped out using semiconductor laboratory 180 nm technology.

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Power Analysis Attack Resistant ASIC Implementation of AES Hardware Accelerator Based on Threshold Implementation

  • 章节

  • 发表日期：

    2025年

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  • P. Saravanan,
  • S. Shanthi Rekha,
  • S. Rajesh Srivatsav,
  • S. Prashanth,
  • M. Aravindh,
  • G. Lakshmanan,
  • R. K. Kirubhas Shankar,
  • A. R. Abdul Rajak

摘要

Cryptography is an essential part of every device involved in the IoT since it ensures the protection of the data against adversaries. The software and hardware implementations of cryptographic algorithms have unwanted leakages that can be leveraged to extract the secret key of the device by a type of attack, namely side-channel attack. This work explores a two-share threshold implementation-based AES hardware accelerator, which is the most efficient technique to withstand first-order power analysis attack with reasonable overhead. The developed ASIC is targeted to work at a frequency of 50 MHz and taped out using semiconductor laboratory 180 nm technology.