The paper details the design and implementation of a 4-bit unsigned binary serial divider using 90 nm CMOS technology. It utilizes Transmission Gate (TG) logic for the division process and offers a comparison with an alternative CMOS logic approach featuring a Kogge Stone adder. The TG Logic implementation boasts a lower transistor count (402) but exhibits higher propagation delay (379.6 femtoseconds) and power consumption (18.42 micro-Watts). In contrast, the CMOS Logic with Kogge Stone adder employs more transistors (792) but results in a shorter propagation delay (494.9 femtoseconds) and lower power consumption (5.987 micro-Watts). The choice between these two methods should be based on the specific application’s needs and priorities.