Effective Low Leakage 6T and 8T SRAM Using CMOS 90 nm Technology
摘要
This study addresses the escalating demand for low-power electronic devices by emphasizing the development of Static Random Access Memory (SRAM) cells with minimized leakage current. The research prioritizes key metrics such as leakage current, read/write stability, access time, and power consumption. To effectively reduce leakage current, reverse-biased FinFETs are employed as efficient switches, creating barriers that impede current flow during idle states. Additionally, power gating techniques selectively disable specific SRAM sub-blocks during inactivity, further reducing static power consumption. This innovative approach, utilizing CMOS 90 nm technology, demonstrates the significance of minimizing leakage current in SRAM cells. The proposed low-leakage 6T and 8T SRAM cells offer a promising solution, contributing to enhanced energy efficiency and performance in memory design. Overall, this research makes notable strides in advancing low-power electronic systems.