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Full adder (FA) circuit implementation commonly employs hybrid logic approach. The effectiveness of the EXOR-EXNOR circuit significantly effects on the latency, power, and driving capabilities of hybrid FA. This article proposes a 10-T XOR-XNOR circuit that operates at fast speed and low power and offers generating outputs with a complete voltage swing while achieving improved delay performance in a simultaneous manner In a Cadence Physical Design tool Virtuoso utilizing 90 nm semiconductor manufacturing process, via simulation the circuit’s performance is evaluated. In comparison to existing EXOR-EXNOR modules, the suggested circuit uses less power. Come up with four FA designs in this article using EXOR-EXNOR circuit that has been proposed, as well as the sum and carry modules that are now available. To assess the driving capabilities, the suggested FAs are implemented into the 8-bit, 4-bit and 2-bit cascaded full adder (CFA) structures. According to the findings, one of the suggested FAs offer the best efficiency for more bits than the other FAs combined.

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Low Power and High Speed Hybrid Adder Design Using 10T XOR–XNOR Logic

  • 会议论文

  • 发表日期：

    2025年

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  • Metta Umasankar,
  • Korada Revanth,
  • Naru Shiva Kumar,
  • Marri Venkatesh,
  • Jami Venkata Suman

摘要

Full adder (FA) circuit implementation commonly employs hybrid logic approach. The effectiveness of the EXOR-EXNOR circuit significantly effects on the latency, power, and driving capabilities of hybrid FA. This article proposes a 10-T XOR-XNOR circuit that operates at fast speed and low power and offers generating outputs with a complete voltage swing while achieving improved delay performance in a simultaneous manner In a Cadence Physical Design tool Virtuoso utilizing 90 nm semiconductor manufacturing process, via simulation the circuit’s performance is evaluated. In comparison to existing EXOR-EXNOR modules, the suggested circuit uses less power. Come up with four FA designs in this article using EXOR-EXNOR circuit that has been proposed, as well as the sum and carry modules that are now available. To assess the driving capabilities, the suggested FAs are implemented into the 8-bit, 4-bit and 2-bit cascaded full adder (CFA) structures. According to the findings, one of the suggested FAs offer the best efficiency for more bits than the other FAs combined.