In Sect. 3.5 , we explained how reconfiguration of programmable interconnect essentially enables time-domain-multiplexing of a limited number of wires across different user designs. We also anticipated that wires could be time-domain-multiplexed between signals of one and the same design. In this chapter, significantly inspired by a lecture by Professor Vaughn Betz (Lecture 13: Embedded NoCs, Time-Multiplexed FPGAs, and Configuration Robustness Alternatives, 2020), we shall motivate the introduction of time-domain-multiplexed interconnect in reconfigurable architectures and attempt to explain how it interacts with the traditional programmable interconnect that has been the main focus of the book. Moreover, we will discuss various aspects of adoption of Networks on Chip (NoCs)—both hard and soft—in FPGAs.