As Moore’s law is no longer delivering the performance improvements that it used to deliver over the past half a century, custom hardware architectures specifically tuned to the requirements of the algorithm that they are intended to implement are increasingly looked at as a promising way forward. At the same time, however, attempts to keep Moore’s law afloat and squeeze out further benefits from technology have made custom chip design prohibitively expensive, with costs reaching half a billion dollars at the 5 nm node. Hence, for a majority of custom hardware designs, actually producing an Application-Specific Integrated Circuit (ASIC) is simply not an option. Instead, they have to rely on reconfigurable integrated circuits such as Field-Programmable Gate Arrays (FPGAs).