The Discrete Cosine Transform (DCT) is a crucial component in numerous image processing applications. The execution of the Discrete Cosine Transform (DCT) is frequently the arithmetic unit that consumes the most time in the field of image processing. The overall efficiency of real-time image applications is affected by the substantial number of Discrete Cosine Transform (DCT) computations involved in image compression. The modification of images using Discrete Cosine Transform (DCT) is frequently challenging to fulfill the demands of real-time processing as a result of the substantial computational burden and software implementation involved. While the Digital Signal Processor (DSP) is indeed robust in its capabilities for digital signal processing, it presents challenges in terms of integrating external peripherals because to its complicated and diverse design, as well as its excessive use of power. On the other hand, the utilization of field programmable gate array (FPGA) is a viable approach to address these limitations, hence facilitating a more streamlined and compact design of the discrete cosine transform (DCT) module, as well as enabling seamless system integration. The majority of image Discrete Cosine Transform (DCT) transformations are frequently carried out on hardware platforms utilizing Field-Programmable Gate Arrays (FPGAs), which may not be considered a cost-effective solution. This study focuses on the implementation of the image Discrete Cosine Transform (DCT) transformation within a System on Chip (SoC) architecture. The utilization of SoC offers several advantages, including enhanced adaptability, simplified peripheral integration, reduced power consumption, and improved communication bandwidth across numerous processors. This functionality becomes beneficial for integration inside a real-time image processing system.