Digital signal processing (DSP) is based on repeated add and multiply operations for real time applications. So, an adder proves to be an important part of DSP systems. It is also an integral part of any processor design in the computer system. So, there should be designed an efficient adder circuit for high speed and low power operation. The combination of different adders can be acceptable for the compact design. In this paper, 12-bit and 14-bit heterogeneous adders consisting of the concatenation of homogeneous sub-adders (Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA)) are proposed. The proposed heterogeneous adder circuits confirm a trade-off between power, delay, and area. These adder architectures are programmed in VHDL and the comparison is done by using VIVADO 2017.1. The combination of 4-bit RCA + 8-bit CLA and 10-bit RCA + 4-bit CLA provide the least total on-chip power consumption of 8.141 W and 9.482 W in 12-bit and 14-bit heterogeneous adders respectively. Similarly, 6-bit CLA + 6-bit RCA and 6-bit RCA + 8-bit CLA provides less area utilization. So, the proposed work with the least power consumption and area utilization can be implemented in advanced digital systems.