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Traditional on-chip filters at 60 GHz often struggle with balancing size, insertion loss (IL), and bandwidth, limiting their effectiveness in miniaturized systems. This paper presents a new electromagnetic (EM) structure for an on-chip bandpass filter (BPF) designed at 60 GHz for System-on-Chip (SoC) integration, achieving high performance and compactness. The proposed design utilizes a mixed coupling technique, incorporating metal–insulator-metal (MIM) capacitors and defected ground structures (DGS) to enhance filter performance. A key design feature is the implementation of folding lines alongside the coupling and integrating MIM capacitors between metal layers M4 and M6 to reduce size and improve bandwidth. The impact of DGS on improving insertion loss (IL) is also investigated. A Complementary Metal–Oxide–Semiconductor (CMOS) process with dimensions corresponding to 0.18 µm technology is utilized in this design. The proposed filter exhibits an IL of 2.9 dB, resonating at 60 GHz with a fractional bandwidth (FBW) of 22%. The compact size of 0.054 mm2 (0.0086λ) makes it suitable for integration into miniaturized systems.

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Miniaturized On-Chip Bandpass Filter Design Using Folded Resonators Loaded by MIM Capacitor for System-On-Chip Integration

  • 会议论文

  • 发表日期：

    2025年

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  • Ahmed Mohamed Sayed,
  • Badr Adel Shawqy,
  • Emad Tammam,
  • Alaa Rabie Mohamed,
  • Anwer S. Abd El-Hameed

摘要

Traditional on-chip filters at 60 GHz often struggle with balancing size, insertion loss (IL), and bandwidth, limiting their effectiveness in miniaturized systems. This paper presents a new electromagnetic (EM) structure for an on-chip bandpass filter (BPF) designed at 60 GHz for System-on-Chip (SoC) integration, achieving high performance and compactness. The proposed design utilizes a mixed coupling technique, incorporating metal–insulator-metal (MIM) capacitors and defected ground structures (DGS) to enhance filter performance. A key design feature is the implementation of folding lines alongside the coupling and integrating MIM capacitors between metal layers M4 and M6 to reduce size and improve bandwidth. The impact of DGS on improving insertion loss (IL) is also investigated. A Complementary Metal–Oxide–Semiconductor (CMOS) process with dimensions corresponding to 0.18 µm technology is utilized in this design. The proposed filter exhibits an IL of 2.9 dB, resonating at 60 GHz with a fractional bandwidth (FBW) of 22%. The compact size of 0.054 mm2 (0.0086λ) makes it suitable for integration into miniaturized systems.