In many FPGA-based systems, only sequential system control structures modeled by finite state machines are actually required. In order to deal with complexity, design time, and verification issues, which are weaknesses of traditional hardware description languages, it may be preferred to describe the control flow behaviorally in software. However, it is reported that high-level synthesis for FPGA often generates inferior results in terms of resources and performance when translating software-style control flow description to hardware. In this paper, the NanoSoftController is proposed as an open-source soft processor, which is optimized for minimal and efficient logic resource usage on FPGA platforms. It is targeted at processing sequential finite state machine functionality in software, featuring a compact ISA for control flow in embedded systems and a tiny accumulator-based data path. Furthermore, an efficient mapping of memory to small distributed LUT RAM instances enables its use as a system state machine controller in even very resource-constrained FPGA designs, requiring only 104 slice LUTs and 76 slice registers in total. However, despite all optimizations, in a case study with high-level synthesis results of three reference software-style control applications, i.e., electronic door lock, smart glucose sensor, and sequential sensor network node, a better resource efficiency could not be shown. We evaluate the negative results and provide lessons we learned from them.