eFPGA redaction is a class of ReBO where the sensitive part of the design is placed on an embedded FPGA; the eFPGA provides the feature of reconfigurability. This is a coarse-grain implementation where a large eFPGA module is placed inside the chip. Similar to employing LUT-based obfuscation, this approach also necessitates a custom tool for partitioning the design, which should be compatible with the IC design flow. This chapter will discuss eFPGA redaction and how it obfuscates a design. The obfuscation process starts with partitioning the design into non-reconfigurable (ASIC) and reconfigurable (eFPGA) parts. There are two major approaches to eFPGA redaction. One approach involves partitioning the design at the HLS/HDL level (soft IP) and implementing it through the design flow. The second approach is partitioning the design at the firm IP level. We will discuss both methods in detail. A PPA overhead is also associated with the use of eFPGAs. Additionally, we will elaborate on the security analysis and aspects related to the physical synthesis with eFPGAs.