SRAM cells used in aerospace applications are more susceptible to soft mistakes as a result of sensitive nodes’ declining critical charge. Single-event upsets, or SEUs, occur in conventional 6T SRAM cells when a radiation particle hits a sensitive node, inverting the data recorded in the cell. Thus, a Soft-Error-Aware Read-Stability-Enhanced Low Power 10T (SARP10T) SRAM cell is proposed in this study to minimize SEUs. Enable appears more practical because this cell is sturdy and operates with a moderate area overhead. However, our analysis reveals that Enable encounters a high rate of write failures with scaled technological parametric fluctuations, rendering this SRAM cell inoperable. Other recently introduced soft-error-aware SRAM cell are compared with SARP10T.Every sensitive node in SARP 10T can retrieve its data in the unlikely case that a radiation assault reverses the node values. It is also possible to recover from single event multi-node upsets (SEMNUs) at its storage node pair by utilizing SARP10T. The ‘0'-storing storage node, which the bit line can access directly during read operations, allows the proposed cell to recover from any disruption, giving it the best-read stability in addition to these advantages. Furthermore, SARP10T has the lowest hold power consumption. Additionally, SARP10T exhibits superior write capabilities and a lower write latency when compared to the majority of the comparative cells. The suggested cell just marginally increases read and write speeds and has a longer read delay to accomplish all these advantages. Modified 10T SRAM cells have been employed to form a 4x4 memory array.