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Floating numbers are represented using IEEE standard 754. IEEE 754 defines formats for representing single-precision and double-precision floating-point numbers, along with rules for performing basic arithmetic operations on these numbers. The standard specifies the following components for both 3single-precision (32-bit) and double-precision (64-bit) floating-point numbers. This project introduces an efficient approach to IEEE 754 floating-point multiplication by implementing it in the logarithmic domain using Logarithmic Number System (LNS). It overcomes the limitations of the traditional floating pointing multipliers. By utilizing logarithmic and antilogarithmic converters, the logarithmic multiplier allows multiplication through addition, enabling support for higher accuracy levels. Floating point multipliers play a vital role in high-power computing applications like image and signal processing. This project approach presents a providing solution to the challenges posed by floating-point multiplication, offering improved performance, reduced delay, and low power consumption for demanding computational tasks in various applications. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E.

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FPGA Implementation of Optimized Floating Point Multiplier Using Minimal Error Logarithmic Approach

  • 会议论文

  • 发表日期：

    2025年

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  • Sheik Jameer Basha,
  • Rakurthi Tharun Sai Eswar,
  • Talluri Sai Vidya,
  • Sannapu Aravind Kumar,
  • Shaik Afreen,
  • B. V. V. Satyanarayana

摘要

Floating numbers are represented using IEEE standard 754. IEEE 754 defines formats for representing single-precision and double-precision floating-point numbers, along with rules for performing basic arithmetic operations on these numbers. The standard specifies the following components for both 3single-precision (32-bit) and double-precision (64-bit) floating-point numbers. This project introduces an efficient approach to IEEE 754 floating-point multiplication by implementing it in the logarithmic domain using Logarithmic Number System (LNS). It overcomes the limitations of the traditional floating pointing multipliers. By utilizing logarithmic and antilogarithmic converters, the logarithmic multiplier allows multiplication through addition, enabling support for higher accuracy levels. Floating point multipliers play a vital role in high-power computing applications like image and signal processing. This project approach presents a providing solution to the challenges posed by floating-point multiplication, offering improved performance, reduced delay, and low power consumption for demanding computational tasks in various applications. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E.