Implementation of Fast Fourier Transform with optimization of adder and multipliers is very important in FPGA implementation. There are many parallel and pipeline techniques were existing for optimizing the subcomponents. This paper presents a new hybrid pipelining architecture, which optimizes the multipliers. It is a dedicated design of real inputs, which is used in many practical applications. The design consists of single processing units for all the stages except the second stage. The memory required for the twiddle factors storage given by the linear life time chart and the analysis of data flow graph gives the optimized result of hybrid pipeline at the stage of insertion. We use ip-core multipliers for the multiplications of twiddle factors in the proposed method. The performance of the proposed method is compared in terms of power consumption which is reduced by the 20% of the existing techniques.