Design and Performance Evaluation of AMBA AHB-Based Master Switches

In modern Network-on-a-Chip (NoC) systems, exchanging data among intellectual property (IP) cores faces challenges such as limited throughput, high energy consumption, signal integrity issues, delays, and synchronization. Enhancing communication methods between IP cores within System-on-Chip (SoC) plays a crucial role in improving chip performance. This paper examines the differences in performance related to power consumption, resource utilization, and timing between master switches using Round Robin Arbitration and Priority-enhanced Arbitration based on the AMBA AHB protocol in Verilog HDL. Then, we evaluate these designs using Questa SIM simulation software. Finally, experimental results indicate that both arbitration methods meet the fundamental requirements of a master switch with the AMBA AHB protocol. Additionally, the Round Robin Arbitration master switch can operate at a higher frequency compared to the Priority-enhanced Arbitration master switch.