This chapter addresses the limitations of enhancing the energy–delay–area product (EDAP) in conventional SRAM technology scaling, highlighting the need for new approaches to improve performance, power, and area (PPA) beyond bitcell scaling. It focuses on subarray design in sub-10-nm nodes, where larger SRAM subarrays show a 56% improvement in EDAP but face challenges such as increased resistance and capacitance, which can lead to write failure. To mitigate these risks, this chapter explores write-ability-aware SRAM subarray optimization, particularly in 14-Å (A14) nanosheet technology. Techniques like divided wordline (DWL) and divided bitline (DBL) are examined to reduce resistance and capacitance in large subarrays at the cost of area penalty. The study offers a framework for optimizing write-ability-aware subarray design, comparing standard and divided designs, and aims to minimize the area penalties while reducing write failure risk at the subarray level. These insights are critical for advancing SRAM design in deeply scaled technologies.