This chapter presents an in-depth analysis of power–performance–area (PPA) in SRAM macros, focusing on subarray and inter-subarray components. Key contributors at the subarray level include local interconnects, such as bitline (BL) and wordline (WL), which face increased resistance and capacitance due to SRAM scaling. This degrades write margins, requiring additional design strategies, such as subarray resizing or resistance–capacitance (RC) reduction techniques. At the macro-level, PPA improvements are driven by subarray area scaling, with the A5 CFET SRAM macro showing a 53–76% enhancement in energy–delay–area product (EDAP) over its A14 NSFET counterpart. However, beyond A5 scaling, further PPA gains plateau due to increasing process and routing complexities. Consequently, this study explores alternative SRAM subarray designs for future PPA improvements. The chapter also discusses optimized designs for SRAM bitcells, subarrays, and macros, based on comprehensive PPA evaluation, with emphasis on inter-subarray interconnect optimization, pin position, and subarray size.