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This chapter provides a comprehensive subarray-level PPA analysis of various device options, ranging from A14 to A3, across high-density (HD), high-performance (HP), and low-power (LP) subarray designs. It details experimental setups, resistance–capacitance (RC) benchmarks, and evaluates hold and read stability under worst-case scenarios. Key challenges, such as channel stress in CFET architectures and its effects on read stability and write margin, are critically analysed to ensure SRAM functionality before conducting further PPA assessments. The chapter also investigates the influence of channel geometry on performance, concluding with detailed PPA benchmarks and strategic recommendations for optimizing subarray size and interconnects. Notably, the HD hybrid CFET SRAM bitcell design shows a significant reduction in RC, improving write margin by 75 mV and read delay by 26% in high-density scenarios compared to sequential and monolithic counterparts, without any bitcell area penalty. These findings underscore the importance of further process development in hybrid CFET technology.

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Subarray-Level Performance-Power-Area Benchmark of CFET SRAM Subarray

  • 章节

  • 发表日期：

    2025年

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  • Hsiao-Hsuan Liu,
  • Francky Catthoor

摘要

This chapter provides a comprehensive subarray-level PPA analysis of various device options, ranging from A14 to A3, across high-density (HD), high-performance (HP), and low-power (LP) subarray designs. It details experimental setups, resistance–capacitance (RC) benchmarks, and evaluates hold and read stability under worst-case scenarios. Key challenges, such as channel stress in CFET architectures and its effects on read stability and write margin, are critically analysed to ensure SRAM functionality before conducting further PPA assessments. The chapter also investigates the influence of channel geometry on performance, concluding with detailed PPA benchmarks and strategic recommendations for optimizing subarray size and interconnects. Notably, the HD hybrid CFET SRAM bitcell design shows a significant reduction in RC, improving write margin by 75 mV and read delay by 26% in high-density scenarios compared to sequential and monolithic counterparts, without any bitcell area penalty. These findings underscore the importance of further process development in hybrid CFET technology.