As SRAM bitcell scaling advances beyond 3-nm technology nodes, various device options such as nanosheet, forksheet, and complementary field-effect transistors (CFETs) have been explored. Among these, CFETs stand out for their superior scalability due to the stacked NMOS and PMOS devices. However, scaling CFET SRAM introduces challenges such as complex interconnect routing and increased parasitic resistance–capacitance (RC). Specifically, the stacked architecture requires taller via connections from the frontside back-end-of-line (BEOL) signals to the bottom pass-gate (PG) devices, which increases bitline (BL) and wordline (WL) capacitances compared to non-stacked SRAM bitcells. This added capacitance limits the power and performance (PP) gains across technology nodes. To address these issues, this chapter introduces hybrid CFETs as a promising design alternative. Hybrid CFETs combine features of sequential (seq) and monolithic (mono) CFETs, using “double-sided interconnects” that allow flexible placement of signal and power rails on different sides of the die. This innovative approach optimizes bitcell routing, resulting in a 41% reduction in wordline resistance, a 25% decrease in bitline capacitance, and a 35% decrease in wordline capacitance compared to seq and mono designs. These improvements have the potential to significantly enhance power and performance (PP) metrics in SRAM designs. This chapter outlines design challenges and strategies to minimize via height for signal connections, emphasizing the advantages of hybrid CFETs in SRAM design. Ultimately, hybrid CFET SRAM bitcells demonstrate significant PP improvements over traditional seq and mono CFET designs.