Scholarlink

In sub-10-nm nodes, increased bitline (BL) resistance in SRAM bitcells presents significant challenges for successful write operations. The higher BL resistance hampers complete BL discharge during writes, while increased leakage currents in half-selected bitcells further degrade write-ability, particularly at higher frequencies. These BL parasitics contribute to a 30% yield loss in SRAM subarrays using 14 Å-compatible (A14) nanosheet technology. Existing methods for determining write margin (WM) fail to adequately account for BL parasitics, leading to overly optimistic predictions of write failures. This chapter introduces an enhanced write-ability methodology to improve write failure predictions in advanced technology nodes. The proposed approach incorporates the time-dependent effects of BL parasitic resistors, capacitors, and pass-gate transistors on WM, along with the negative bitline (NBL) write-assist technique. A detailed comparison between conventional BL write margin (BLWM) methods and the proposed methodology is presented, demonstrating its advantages in ultra-scaled nodes.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Extended Write Margin Methodology for SRAM Subarray in Resistance-Dominated Technology Node

  • 章节

  • 发表日期：

    2025年

查看全文
  • Hsiao-Hsuan Liu,
  • Francky Catthoor

摘要

In sub-10-nm nodes, increased bitline (BL) resistance in SRAM bitcells presents significant challenges for successful write operations. The higher BL resistance hampers complete BL discharge during writes, while increased leakage currents in half-selected bitcells further degrade write-ability, particularly at higher frequencies. These BL parasitics contribute to a 30% yield loss in SRAM subarrays using 14 Å-compatible (A14) nanosheet technology. Existing methods for determining write margin (WM) fail to adequately account for BL parasitics, leading to overly optimistic predictions of write failures. This chapter introduces an enhanced write-ability methodology to improve write failure predictions in advanced technology nodes. The proposed approach incorporates the time-dependent effects of BL parasitic resistors, capacitors, and pass-gate transistors on WM, along with the negative bitline (NBL) write-assist technique. A detailed comparison between conventional BL write margin (BLWM) methods and the proposed methodology is presented, demonstrating its advantages in ultra-scaled nodes.