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This chapter presents a comprehensive simulation framework for evaluating margin, power, performance, and area (PPA) in deeply scaled SRAM designs. The framework, covering bitcell, subarray, and macro-levels, is crucial for optimizing PPA. We provide detailed modelling and simulation setups for various transistor architectures, including nanosheet, forksheet, and CFET, across advanced technology nodes (14 Å, 10 Å, 5 Å, 3 Å). Additionally, this chapter describes simulation methodologies for parasitic extraction (PEX), Monte Carlo analysis, and SRAM macro-level evaluation. This chapter introduces key concepts such as data retention, leakage, read/write operations, stability, and assist techniques. A framework for analysing write failure within SRAM design in deeply scaled nodes is also developed.

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SRAM Operations and Simulation Methodologies at Bitcell, Subarray, and Macro Levels

  • 章节

  • 发表日期：

    2025年

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  • Hsiao-Hsuan Liu,
  • Francky Catthoor

摘要

This chapter presents a comprehensive simulation framework for evaluating margin, power, performance, and area (PPA) in deeply scaled SRAM designs. The framework, covering bitcell, subarray, and macro-levels, is crucial for optimizing PPA. We provide detailed modelling and simulation setups for various transistor architectures, including nanosheet, forksheet, and CFET, across advanced technology nodes (14 Å, 10 Å, 5 Å, 3 Å). Additionally, this chapter describes simulation methodologies for parasitic extraction (PEX), Monte Carlo analysis, and SRAM macro-level evaluation. This chapter introduces key concepts such as data retention, leakage, read/write operations, stability, and assist techniques. A framework for analysing write failure within SRAM design in deeply scaled nodes is also developed.