Network-on-chip (NoC) is a verbal exchange protocol for incorporated circuit and System-on-Chip (SoC) systems. It correctly integrates a packetswitched network of routers and switches. Compared to conventional communique structures, NoC offers scalability, modularity, high performance, flexibility, and capability performance. NoC is important in present-day chip layout as it addresses issues of performance, scalability, and strength intake. It improves overall performance via the usage of high bandwidth and occasional latency connections. It allows for scalability via validating more than one component and allows for destiny expansion. The purpose of the paper is to analyze the Network on-chip (NoC) layout and examine one-of-a-kind topologies for efficient on-chip verbal exchange.