LaRed: An LSTM Accelerator on RISC-V-Based Edge Devices

The rapid development of the Internet of Things (IoT) has imposed considerable strain on server systems, leading to a transition towards the integration of artificial intelligence (AI) into edge devices. In this paper, we propose LaRed, an LSTM accelerator designed for RISC-V-based edge devices. LaRed addresses this challenge by optimizing LSTM computations through data reuse and enhanced Multiply-Accumulate (MAC) units. LaRed is implemented and evaluated on a PynqZ2 FPGA board (XC7Z020). Experimental results obtained using the MNIST dataset demonstrate that the LaRed system outperforms the original Ibex-based System on Chip (SoC) by a significant factor of over 97x in terms of inference time. Despite a slight reduction in accuracy due to the model quantization to 8 bits for hardware resource conservation, the LaRed system still achieves an accuracy rate of 90.23%, accompanied by low power consumption of 376 mW. Moreover, compared to previous FPGA implementations of LSTM networks, LaRed exhibits superior resource utilization, outperforming the best implementation by up to 2x.