A WalaP-Based CNN Architecture for Real-Time Edge Computing Devices in IoT Systems

Recently, the emergence of the RISC-V open-source ISA has opened up new possibilities for developing customized IoT platforms. The advancements in neural networks have significantly enhanced the accuracy of various intelligent applications, including image processing and voice recognition. In this paper, we propose a WalaP-based CNN architecture (Wallace adder tree with final stage Prefix adder) and validate it using the MNIST handwritten dataset. The WalaP-based CNN architecture is implemented with a sliding-filter for convolution and parallel computation of Multiplication and Accumulation (MAC) operations, resulting in an optimized hardware architecture with reduced arithmetic operations and faster computations for high-performance edge computing systems. The developed architecture, with a precision of 32-bit float, is implemented using High-Level Synthesis (HLS) on the Xilinx Virtex-7 FPGA VC707 board. It achieves a significant improvement in speed, processing frames in just 0.0206 ms/frame, with a GOPS of 71.62. The system also achieves high accuracy, with performance of up to 98.55%.