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The available parallelism and heterogeneity of emerging computer systems must be exploited for being able to process the huge amounts of data produced every day. As a consequence, we observe an increasing research interest in accelerating database query processing on multi-cores and attached co-processors like Graphics Processing Units (GPUs) and Field-Programmable Gate Arrays (FPGAs). This chapter presents ReProVide, an approach combining near-data processing and FPGA-based acceleration. The System-on-Chip (SoC) architecture of ReProVide including a flexibly reconfigurable FPGA can load and execute hardware accelerators for various operators on relational and streaming data. Moreover, we present novel DBMS techniques for partitioning query-execution plans between a host and Reconfigurable data-Provider Units (RPUs) and for mapping operators onto RPUs by means of hardware reconfiguration.

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ReProVide: Query Optimization and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis

  • 章节

  • 出版模式：

    开放获取

  • 发表日期：

    2025年

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  • Tobias Hahn,
  • Maximilian Langohr,
  • Andreas Becher,
  • Lekshmi Beena Gopalakrishnan Nair,
  • Klaus Meyer-Wegener,
  • Jürgen Teich,
  • Stefan Wildermann

摘要

The available parallelism and heterogeneity of emerging computer systems must be exploited for being able to process the huge amounts of data produced every day. As a consequence, we observe an increasing research interest in accelerating database query processing on multi-cores and attached co-processors like Graphics Processing Units (GPUs) and Field-Programmable Gate Arrays (FPGAs). This chapter presents ReProVide, an approach combining near-data processing and FPGA-based acceleration. The System-on-Chip (SoC) architecture of ReProVide including a flexibly reconfigurable FPGA can load and execute hardware accelerators for various operators on relational and streaming data. Moreover, we present novel DBMS techniques for partitioning query-execution plans between a host and Reconfigurable data-Provider Units (RPUs) and for mapping operators onto RPUs by means of hardware reconfiguration.