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Following the recent advances in open hardware generally, and RISC-V architectures particularly, we analyse the performance of transformer encoder inference on three low-power platforms with this type of architecture. For this purpose, we conduct a detailed profile of the inference process for two representative members of the BERT family, identifying the main bottlenecks and opportunities for optimisation on three RISC-V processors equipped with floating-point SIMD (single instruction, multiple data) units: XuanTie C906, C908, and C910.

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Performance Analysis of BERT on RISC-V Processors with SIMD Units

  • 会议论文

  • 发表日期：

    2025年

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  • Héctor Martínez,
  • Sandra Catalán,
  • Carlos García,
  • Francisco D. Igual,
  • Rafael Rodríguez-Sánchez,
  • Adrián Castelló,
  • Enrique S. Quintana-Ortí

摘要

Following the recent advances in open hardware generally, and RISC-V architectures particularly, we analyse the performance of transformer encoder inference on three low-power platforms with this type of architecture. For this purpose, we conduct a detailed profile of the inference process for two representative members of the BERT family, identifying the main bottlenecks and opportunities for optimisation on three RISC-V processors equipped with floating-point SIMD (single instruction, multiple data) units: XuanTie C906, C908, and C910.