In a classical charge pump (CP) phase-locked loop (PLL) with a phase frequency detector (PFD), the PFD compares the timing error between the reference clock and feedback clock edges and extracts their timing differences. The phase detection is thus done in the time domain. In a sub-sampling(SS) PLL, the sub-sampling phase detector converts the timing error into sampled voltage difference. The phase detection is thus done in voltage domain. Due to the high slope of the sampled clock, the SSPLL can achieve very high phase-detection gain and thus low in-band phase noise. This chapter first reviews the development of the SSPLL, then presents a fractional-N sampling PLL architecture, where not only phase detection, but also quantization noise cancellation is done in the voltage domain. This simplifies the PLL’s critical phase detection path, saves power, reduces noise sources, and improves the overall linearity. A 3.3–4.5-GHz PLL design in 40-nm CMOS was demonstrated to achieve a 292-fs rms jitter, integrated from 10 kHz to 10 MHz while consuming 2.4 mW, leading to a PLL FoM of −246.9 dB. The in-band fractional spur is −54 dBc, and the PLL occupies a core area of 0.36 mm2.