Over the past two decades, all-digital techniques for RF frequency synthesis have gained significant interest. In this chapter, we will review the all-digital phase-locked loop (ADPLL) architecture (also known as the phase-domain ADPLL and retrospectively classified as the counter-based ADPLL) followed by new techniques that help push the jitter performance. To relax the stringent requirements of traditional time-to-digital converters (TDC) in conventional ADPLLs, a digital-to-time (DTC)-assisted architecture has been introduced. This significantly shortens the required TDC range while increasing its resolution to help achieve low jitter while consuming low power. In this chapter, we present oversampling and charge-sharing locking techniques for frequency synthesis that help to achieve low rms jitter.