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This paper presents the design of a low-power logic gate approximate adder based on an inexact full adder. Simulation results show that the proposed adder improves the accuracy over approximate adders by 27% in terms of mean square error (MSE) while achieving a power reduction of 8% demonstrated by synthesis. Moreover, when compared to the exact adder, the proposed circuit achieves a power reduction of up to 40% in the case of a 16-bit adder with 14 approximated bits.

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Low Power Design of Approximate Adders Based on Inexact Full Adder

  • 会议论文

  • 发表日期：

    2025年

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  • Ali Ibrahim,
  • Fatima Bzeih,
  • Oussama Srour,
  • Zeinab Hijazi,
  • Orazio Aiello

摘要

This paper presents the design of a low-power logic gate approximate adder based on an inexact full adder. Simulation results show that the proposed adder improves the accuracy over approximate adders by 27% in terms of mean square error (MSE) while achieving a power reduction of 8% demonstrated by synthesis. Moreover, when compared to the exact adder, the proposed circuit achieves a power reduction of up to 40% in the case of a 16-bit adder with 14 approximated bits.