VLSI Implementation of Secured S-Box Design for Light-Weight Block Ciphers in Low Area Applications

Embedded devices and Internet of Things (IoT) applications are becoming increasingly popular in today's world. The resource-constrained devices prefer to employ light-weight block ciphers for security. When light-weight cryptographic algorithms are used to provide security in these devices, they have a tendency to leak some information. Gain of this information helps the attacker to retrieve the key. One such attack that has gained increased attention is power analysis. Boolean masking is a countermeasure against power analysis attacks. The substitution box (S-Box) of lightweight ciphers PRESENT, LED, GIFT, KLEIN, and RECTANGLE has been considered here. We present a secured compact S- Box that consumes less power and area. The results of implementation on 45nm and 90nm technology application-specific integrated circuits (ASIC) validate our state. This design is suitable for low area applications and devices like smart cards, Radio frequency identification (RFID). Furthermore, Masking algorithms are used to obliterate information making it impossible to recover the original data. The suggested compact S-Box of these low weight ciphers was examined and compared to the protected and unprotected gate equivalents in terms of area, power consumption, and latency.1 to 5% reduction of area and 7% reduction of delay is achieved for protected compact S-Box when compared with un-protected non-compact S-Box.