Balanced State Splitting of Finite State Machines for FPGA Implementations of Control Units

A balanced approach to splitting procedures for finite state machines that are implemented in field programmable logic arrays is proposed. This method incorporates optimization criteria, including power consumption and speed of operation, at the initial stages of the finite state machine's synthesis. Additionally, the method considers the technological aspects of programmable logic and the state encoding method. To calculate the transformation quality ratio, the estimates of the power and speed parameters are considered, and the user has the option to choose the direction of optimization by setting the weights for each criterion. The approach to estimate the optimization criteria values is presented and the experimental results are discussed.