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Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility

  • Mohammed Nabeel,
  • Deepraj Soni,
  • Ramesh Karri,
  • Michail Maniatakos

摘要

Fully Homomorphic Encryption (FHE) promises complete input privacy by allowing computation on encrypted data at the expense of high computation. FHE hardware accelerators improve performance with large and densely packed computing units, which could potentially create thermal hot spots because of high power consumption. Therefore, it is necessary to reduce the area and power consumption of the accelerator and its most critical module, i.e., the modular multiplier. In this work, we use the fact that, for FHE computation, the modulus should be of a specific form with its lower bits constrained to a decimal value of one. We examine the impact on area and power of two popular modular multiplication algorithms, Barrett and Montgomery, with different constrained widths for different modulus sizes. Our experiment results show that modular multipliers with constrained width can reduce area by 20% and power consumption by 15%-to-25%. We also propose an approximation for the number of prime moduli available with such a constrained modulus.