3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
摘要
This paper presents a flash Time Domain ADC with T/H amplifier, Voltage Controlled Delay Line and Time to Digital Converter. The design is operating at 3.125 GS/s with 4.9 ENOB and a Walden figure of merit of 109 fJ/Conversion. Automatic calibration means are provided as well. For measurements purposes, an integrated memory is provided. It consumes 16.2 mW from a 1 V supply. It was realized in the 45 nm PDSOI from Global Foundries.