Improving Reed Solomon (RS) Decoder Using Two Simultaneously Modified Blocks of Chien Search and Syndrome

Currently codes correctors of errors are used in endless number of tasks from emitter to receptor in transmission chains. This paper proposes efficient RS decoder. The main idea of this work is to design theses decoders based tow simultaneous modified chien search block based factorization methods and parallel syndrome block. Moreover, we discuss how this contribution can be improved the performance and the efficiency of the proposed circuit. The new chien search and syndrome blocks used by the proposed decoders require much more complexity and number of iterations respectively those most existing classical blocks. The proposed decoders will be developed by using the hardware description language (VHDL) and the simulations tests of these circuits are done in Xilinx software. The design is evaluated in terms of number of iterations and FPGA resources. Further, the results obtained show that the proposed decoders have efficient compared to existing decoders using classical chien search and syndrome blocks.