ImSPU: Implicit Sharing of Computation Resources Between Vector and Scalar Processing Units

SIMD extensions instruction sets are widely adopted in modern processors, leveraging the data-level parallelism to provide significant performance speedups. However, the throughput of SIMD instructions relies on the number of vector processing units, the scalar processing units are underutilized in performing SIMD operations. This paper presents a SIMD processor architecture, ImSPU, which enables implicit sharing of computation resources between scalar and vector processing units. This architecture effectively leverages the scalar processing unit for SIMD operations, thereby boosting parallel computing capabilities. Unlike explicit sharing, which requires the issuance of scalar instructions, implicit sharing remains transparent to software developers and compilers, eliminating the need for code modifications. Furthermore, implicit sharing necessitates minor modifications to the processor architecture and is straightforward to implement in hardware. In comparison to traditional SIMD processors, the proposed implicit sharing architecture achieves substantial performance gains while incurring minor hardware overhead.