A Formal Framework for Digital Twin Modeling, Verification, and Validation

In today’s technological landscape, Digital TwinsDigital twin have emerged as pivotal technologies, offering unprecedented opportunities for innovation and optimization across various industries. Despite numerous on-going research and development initiatives, the verification and validationVerification and validation (V&V) of the Digital Twin (DT) remains a major scientific obstacle. In order to disambiguate the DT concept (as various interpretations exist), this chapter first formalizes it, using the Discrete Event System SpecificationDescreet Event System Specification (DEVS) approach. Then, following a review of the state-of-the-art in V&V, it examines three avenues for developing methodologies for V&V of DTs: software engineeringSoftware engineering-based V&V, simulation-based V&V, and formal methodVerification and validation by formal method-based V&V. That way, this chapter provides a framework for DT understanding and a roadmap for future research on DT V&V.