Architecture-Aware Optimization Strategies for Instruction Selection in DSP Compilers

This paper explores the problem of instruction selection optimization in LLVM backend code for transforming platform-independent intermediate code into high-quality target platform instructions. The instruction selection process is divided into two problems: pattern matching and pattern selection. We propose a novel architecture-aware optimization strategy that leverages the features of digital signal processors (DSPs) to improve the efficiency and performance of instruction selection. Our approach involves analyzing the characteristics of DSP architectures to guide the selection of optimal instructions. We evaluate our approach on a set of benchmarks and demonstrate significant improvements in both execution time and code size compared to existing LLVM optimization techniques. Our results show that architecture-aware optimization strategies can effectively enhance instruction selection in DSP compilers, leading to better performance and reduced energy consumption in real-world applications.