On-the-Fly CT Image Pre-processing on MPSoC-FPGAs

Due to the increasing number of tumors, new interventional Computed Tomography (CT) procedures have been proposed that aim to optimize workflow, time-effective diagnosis and treatments. To support tumor ablation procedures, CT scanners must pre-process 2D projections and reconstruct 3D slices of the human body in real time, while data are acquired. This paper proposes a lightweight processing architecture for MPSoC-FPGA that performs the “CT pre-processing phase” on the fly; this phase consists of the pixel processing of 2D images. It is also suitable for exploring different data formats that can be selected at design time to improve performance while keeping image quality. This article focuses on the cosine and redundancy weighting steps, which can not be implemented following the standard method on embedded MPSoC-FPGA, due to the high resource utilization costs of their arithmetic operations. Therefore, this work proposes different optimizations that result in a reduction of the number of operations to compute and the amount of on-chip memory required in comparison to the standard algorithm. Finally, the proposed architecture has been implemented and instantiated within a Control Data Acquisition System (CDAS) architecture running on the XC7Z045 AMD-Xilinx MPSoC-FPGA and integrated into an open-interface CT scanner assembled in our laboratory. Here, the optimized weighting steps use up to 33.8 times fewer DSPs than the implementation based on the standard solution. Furthermore, it adds only 80 ns of latency, making it 7.9 times faster than the implementation based on the standard solution.