Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding

This paper focuses on implementing and optimizing a 2D Integer Discrete Cosine Transform (DCT) hardware accelerator to provide an efficient and flexible solution for the H.266 video compression standard. Unlike previous standards, H.266 introduces additional complexities in the 2D DCT computation, such as support for non-square blocks and high frequency removal. Our proposed design offers a versatile implementation method for the 2D Integer DCT hardware at very high speed. Our approach aims to provide a flexible and efficient solution, achieving better results than other methods. The results were tested on the Stratix 10 FPGA, utilizing 35,799 ALMs at the frequency of 353.23 MHz, and throughput reached 11,482.77 Mega pixels/s supporting video resolutions up to 16K@60fps. The data was also verified by using VTM reference software [1].