Design and Implementation of Energy Efficient Approximate Three Operand Binary Adders

This paper explores various types of Adders. Adders are used in digital integrated circuit design as digital components. Modular arithmetic is carried out with various pseudorandom bit generator algorithms (PRBG) and cryptography using a three-operand binary adder. The method most frequently used to accomplish the three-operand addition is the carry-save adder (CSA). However, there is a significant propagation delay as a result of the ripple-carry stage in the CSA. The three-operand binary addition also uses Han Carlson adder. It considerably decreases the crucial path time at the expense of more hardware. Reverse Carry Propagate Full Adders (RCPFA) are used in place of full adders in the proposed design. This study compares seven different types of three operand adder architectures that are implemented in FreePDK 32nm static CMOS technology. The architectures are designed to operate at 0.9V for 32-bit input vectors, and the comparison is based on metrics such as cell path latency, power, and power delay product (PDP).